1. Field of the Invention
The present invention relates to techniques for determining the timing of an IC design. More specifically, the present invention relates to a method and apparatus for determining the post-physical-optimization timing of an IC design without performing physical optimizations.
2. Related Art
Physical implementation tools for integrated circuits (ICs) are typically used to improve the performance of a design and the predictability of the design flow, and in doing so, these tools improve the productivity of the designer.
Designers typically require early feedback regarding the feasibility of various design styles and floorplans during design exploration. A fast and accurate prediction of the post-physical-optimization timing can (1) reduce the turnaround time of floorplan redesign, (2) reduce the number of design iterations, and (3) eliminate late design-cycle surprises. Hence, it is desirable to obtain a fast and accurate prediction of the post-physical-optimization (i.e., post-physical synthesis) timing of the design at an early stage in the design process.
Moreover, large designs (e.g., greater than five million gates) often cannot be optimized in a flat layout due to computing resources constraints. These designs are often partitioned or designed hierarchically, so that smaller sub-designs can be optimized individually. One key task during the partitioning process is budgeting, which involves properly assigning timing constraints to the sub-designs so that the sub-designs are neither over-constrained nor under-constrained. For example, in FIG. 3, while optimizing the path between flip-flops 300-301, if the path between flip-flop 300 and point 304 is easy to optimize, while the path between point 302 to flip-flop 301 is hard to optimize, a timing budgeter typically assigns a more stringent timing constraint to the former path, while assigning a more lenient timing constraint to the latter path. A quick and accurate post-physical-optimization timing prediction can quantify the “potential for optimization” of a path, which facilitates more accurate time budgeting.
Furthermore, timing closure can be achieved by having good placement of cells and hard macros. Timing-driven placement places together cells that have large delays between them, which reduces the delays. A timing-driven placer typically considers the “potential for optimization” of the nets and cells, so that nets that are hard to optimize are shortened, and cells that are hard to optimize are placed together.
Presently, the only way to determine the post-physical-optimization timing of an IC design is to first perform physical optimization on the IC design. Unfortunately, physical optimization can sometimes take days to complete. If a timing error is discovered after performing physical optimization, the design must be changed before physical optimization is performed again. This iterative process is costly.
Hence what is needed is a method and apparatus for determining the timing of an IC design without the problems described above.